The present invention generally relates to digital data processing system architectures and more specifically relates to control of single instruction stream multiple data stream (SIMD) machines.
In the normal SIMD machine, a single control structure is used to manage a number of parallel processing structures, called arithmetic units. The SIMD architecture can be employed when parallelism is inherent in the processing problem. Considerably improved performance may be realized because of the parallel processing (i.e., SIMD) approach whereby many time consuming arithmetic operations may be accomplished in a parallel rather than a serial fashion. The reader is urged to consult Kenneth J. Thurber, "Large Scale Computer Architecture," Hayden 1976, for a more rigorous discussion of SIMD architectures.
The SIMD architecture is also likely to be advantageous from a cost standpoint for those tasks having substantial parallelism. This occurs because of the advantages inherent in making a number of small parallel rather than one large serial processing element for a given size processing task.
Despite these advantages, parallel processing using an SIMD architecture has two major problems which may preclude its use. The first is a characteristic of the processing task to be accomplished. Put simply, the task may not involve sufficient parallelism to make an SIMD approach practical. A solution to this problem is not within the scope of this disclosure and so will not be addressed further.
The second probjem is a function of the control architecture chosen. For a single instruction stream to control a number of arithmetic units each processing one of the multiple data streams, the arithmetic units must be tightly coupled to one another and to the overall control structure. This is usually accomplished using a master or control processor which responds to the single instruction stream by controlling or managing the individual arithmetic units.
Historically, the functions of the control processor have tended to grow in complexity necessitating a more and more powerful control processor. Yet, the control processor continues to be the major performance limiting element because a part of its functions must be performed in serial fashion. The tendency has been to make the control processor responsible for all transfers of control information and data to or from the arithmetic units. This tends to severely limit performance particularly if these transfers are all accomplished in a serial fashion. A partial solution to the problem is assigning responsibility for managing some of the transfers to the arithmetic unit involved in the transfer. However, this approach may also limit performance because of the processing capacity of the arithmetic units consumed by housekeeping activities.